1. Field of the Invention
The present invention relates to photodiodes having p-n junctions, and particularly relates to a photodiode suitable for optical communication, an optical receiver device including the photodiode, and a method of making the photodiode.
2. Description of the Related Art
A typical widely used photodiode module is accommodated in a coaxial type metal package with a lead pin. A front illuminated photodiode ID) chip is fixed to the surface of a stem. A lens and an optical fiber are fixed in axial alignment on the PD chip, and the module is sealed hermetically. Signal light having propagating through the optical fiber is converged by the lens and is incident on the top of the PD, which converts the light into a photocurrent. The device is tightly sealed in the metal package to ensure stable characteristics and a prolonged lifetime with high reliability. However, such a photodiode module inevitably requires axial alignment and use of an expensive metal package, which results in high material and process costs and bulkiness. Thus, inexpensive and compact photodiodes are required.
For the purpose of reduced costs, a planar lightwave circuit (PLC) type of photodiode has been developed in which a rear illuminated PD chip is mounted onto an Si (silicon) substrate. FIGS. 9 and 10 show a structure of a known rear illuminated PD. An absorption layer is provided on a substrate and a p-n junction is formed such that a p-electrode and an n-electrode are respectively provided on the top and the bottom of the device. The semiconductor layers are composed of various materials depending on the wavelength of incident light.
For example, in a photodiode 7 having a p-n junction used in optical communication in the wavelength range of 1.0 μm to 1.6 μm, an n-InGaAs absorption layer 2 is epitaxially grown on an n-InP substrate 1, and a p-type impurity such as zinc is diffused into the center of the n-InGaAs absorption layer 2 to form a p-type region 3. A p-electrode 4 is provided on the p-type region 3 and an annular n-electrode 6 is formed on the bottom of the n-InP substrate 1. The n-electrode 6 has an annular shape so that light is incident on the rear face (bottom face). Since the light is not incident on the top face, the p-electrode 4 has a circular shape having a large area. A passivation film 5 made of, for example, SiN is provided around the peripheral region of the p-electrode 4 on the top face. In this device, the passivation film 5 also covers a peripheral region 19 of the top face of the crystal. Referring to FIG. 9, the p-electrode 4 and the passivation film 5 are concentric on the top face. An n-InP cap layer may be provided on the n-InGaAs absorption layer 2 in some cases.
A boundary 12 between the n-InP substrate 1 and the n-InGaAs absorption layer 2 is not a p-n junction and can be exposed to side faces 13 of the chip. A dished boundary between the p-type region 3 and the n-InGaAs absorption layer 2 is a p-n junction 14. The p-type region 3 is formed by impurity diffusion through a mask on the peripheral region of the chip; the dished boundary is thereby formed. The end 15 of the p-n junction 14 is exposed to the top face, as opposed to the side faces. The end 15 of the p-n junction 14 is covered with the insulative passivation film 5 to prevent deterioration of the device starting from the p-n junction end 15.
Signal light is incident on a rear opening 17. A reverse bias from an external circuit is applied between the p-electrode (anode) 4 and the n-electrode (cathode) 6. The signal light that enters the p-n junction 14 through the absorption layer 2 generates electron-hole pairs. An electric field generated by the reverse bias moves the carriers to generate a photocurrent. The photocurrent is taken out into the external circuit and the optical signals can be converted into electrical signals.
FIGS. 11 and 12 are respectively a plan view and a longitudinal cross-sectional view of a surface mounting optical receiver device including the rear illuminated PD 7. V-shaped grooves, markers, and a metallized pattern for forming a number of chips are formed on a large disk Si wafer along the cleavage by photolithographic processes, such as vapor deposition, sputtering, or etching. The wafer is cut along the cleaved surface into rectangular chips with predetermined sizes. Each chip is called an Si bench 8.
A V-groove 20 extends to the midway of the rectangular Si bench 8 along the central axis parallel to the long sides of the Si bench 8. A metallized pattern is provided on the Si bench 8 by printing or vapor deposition. When an optical transmission medium is an optical fiber, the V-groove is used. When the optical transmission medium is a light waveguide, the light waveguide is preliminarily formed on the Si bench. Although the optical transmission medium may be a light waveguide, in the following description, it is an optical fiber and the V-groove is provided. The above-described process is a wafer fabrication process.
The following is a chip fabrication process after a wafer is separated into Si benches. A rear illuminated PD 7 is fixed on a metallized pattern 21 at the edge of the V-groove according to a marker. The annular n-electrode 6 at the bottom of the PD 7 is fixed to the metallized pattern 21 with solder. The bonded interface between the PD 7 and the Si bench 8 has a U shape and is stable, although the bonding state is not clear in FIG. 12. A structure in which the PD 7 is mounted on the Si bench 8 is called a submodule 29.
An optical fiber 9 is placed and fixed with a resin (not shown) in the V-groove 20. The V-groove 20 has an inclined reflective plane 22 at the end. The V-groove 20 and the reflective plane 22 are filled with a transparent resin (not shown). The signal light 23 emerging from the optical fiber 9 is reflected by the reflective plane 22. The reflected light 24 is refracted at the rear face of the PD 7, and the refracted light 25 reaches the p-n junction in the center of the light receiving section to generate a photocurrent. The light from the optical fiber propagates parallel to the Si substrate plane, and the light incident surface of the PD is parallel to the optical axis. Thus, the reflective plane 22 is essential for directing the light toward the PD.
FIGS. 11 and 12 show an assembly of the submodule and the optical fiber. The assembly is placed onto a lead frame (a thin metal plate having many leads), the metallized pattern is wire-bonded with the leads, and the entity with the Si bench and the lead frame is molded into, for example, an epoxy resin to form a plastic-packaged device, as shown in FIG. 8.
A reason for the use of the Si bench 8 as a receptacle of the chip and optical fiber is that fine structures such as oxide films and a metallized pattern can be readily formed by matured Si semiconductor production processes. Furthermore, the V-groove 20 and the reflective plane 22 can be precisely formed by anisotropic etching of the single-crystal silicon. In addition, markers for fixing the chip can be precisely formed. The single-crystal silicon having such advantages is preferentially used.
The inventors of the present invention have proposed various surface mounting PD modules including the rear illuminated PD chips. For example, Japanese Unexamined Patent Application Publication No. 2000-105327 entitled “OPTICAL RECEIVER MODULE” discloses a PD module in which a V-groove having a reflective plane is formed on an Si bench, an optical fiber is fixed onto the V-groove, a rear illuminated PD chip is placed onto the Si bench face above the reflective plane at the end of the optical fiber, and the assembly is covered with a transparent resin.
Such a surface mounting photodiode module is prepared as follows: Rectangular chips (Si benches or Si substrates) are prepared by cutting an Si wafer, and a PD chip is provided onto each Si bench.
Japanese Unexamined Patent Application Publication No. 8-264748 entitled “OPTICAL WAVEGUIDE INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF” discloses an invention of a light-emitting device (LD) module including an LD. A deep recess with a depth D and a rectangular groove adjoining the recess are formed on an Si bench by etching. A thin LD with a thickness d is placed on the deep recess (d<D), and the assembly is covered with a transparent resin. Another transparent resin having a slightly different refractive index is used for the rectangular groove to provide a core-clad structure, so that the end of the core connects to an LD stripe (light emitting layer).
Such a chip-embedded LD module is also prepared as follows: Grooves, patterns, and markers are formed on an Si wafer, and the wafer is cut into chips (Si benches). An LD is placed onto each Si bench and a transparent light waveguide is formed. After wire bonding, the entity of the assembly is covered with a transparent resin.
Japanese Unexamined Patent Application Publication No. 8-264748 discloses a method for making a combined LD module on an Si substrate. A plurality of LD modules, for example, five LD modules are transversely arranged and are driven with one driver IC.
FIG. 13 is a plan view of an Si wafer in the final step of such a wafer fabrication process. Many chip units 32 are formed on an Si wafer 30. A common driver IC 31, a plurality of LDs 33, and a plurality of resin waveguides 34 are formed on each chip unit 32. These LDs 33 are wire-bonded to the common driver IC 31, and the light waveguides and the LDs are covered with a transparent resin. The Si wafer 30 is cut along vertical scribing lines 36 and horizontal scribing lines 37 into individual chip units 32. Each chip unit 32 is provided with five resin waveguides, five LDs, a common driver IC, wiring (wire bonding), and a transparent resin cover. Thus, the chip unit 32 can be directly mounted to a lead frame and be accommodated into a package.
One Si wafer includes several hundred chips (Si benches) of photodiode modules. If PD chips are simultaneously mountable, the process time can be significantly reduced. However, only a PD mounting step can precede the chip-dicing step. A wire bonding step and a resin application step must be performed after the chip-cutting step.
It is difficult to transfer a wired wafer after wire bonding and to scribe it by using a scriber without damaging the wires.
We will now forecast new problems that would arise if the PD was mounted in a step of the wafer fabrication process for the surface mounting PD module, although no example of a scribing step after mounting of the PD onto the Si wafer is actually known.
In conventional methods, chip units or submodules including V-grooves and metallized patterns are formed on an Si wafer and are cut along vertical and horizontal scribing lines. In the scribing step, the Si wafer is fixed and is diced along scribing lines with a rotating blade while a cutting solution is being supplied. The chips are then cleaned.
Since the Si wafer has a considerable thickness, chips may be damaged by the mechanical dicing and will be contaminated by dicing chips. Although the contaminations such as dicing chips and cutting solution residue can be removed by cleaning to some extent, sticky fine contaminations cannot be easily removed.
If the PD chips are fixed to a wafer before dicing, the PD chips will also be subjected to shock from dicing. Such shock has not been considered with respect to PDs made by the conventional method. When dicing is performed along the scribing lines on the Si wafer, chips may damage the passivation films of the PD chips. Furthermore, mobile ions such as sodium ions may adhere. Removal of the contaminations such as sodium ions adhered to the PD chips is extremely difficult. Such contaminations may reach the ends of the p-n junction and may impair the function of the p-n junction. As a result, a dark current that flows when no light is incident in a reverse bias mode may increase, thus increasing noise.
FIG. 14 is a cross-sectional view of a rear illuminated PD 7 after dicing in the case where the PD was placed on an Si bench 8 and dicing was performed. Many contaminations 40 adhere to the top face of the PD 7 as a result of dicing the Si wafer provided with the PD. Such contaminations would adhere to the side and rear faces of the PD 7 but they are not depicted in the drawing. Contaminations 40 spread over the p-electrode 4, the passivation film 5, and a gap 18. In FIG. 14, the contaminations 40 represented by circles include fine particles such as sodium ions, as well as the dicing chips and cutting solution particles. Shock from dicing may cause damages 41 on the thin insulative passivation film 5. Furthermore, the contaminations 40 may penetrate into narrow gaps between the crystal layer and the passivation film 5. In particular, sodium ions will readily penetrate into such narrow gaps.
Although the passivation film 5 covers the ends 15 of the p-n junction, the contaminations 40 may reach vicinities 42 (surrounded by broken lines) of the end of the p-n junction from an exposed portion 18 through a gap between the passivation film 5 and the crystal surface. If so, a dark current generated by leakage of carriers from the p-n junction increases, resulting in an increase in noise and deterioration of receiving performance. Such a dark current may cause malfunction of the device at high environmental temperatures, since the thermal changes of dark current is significant.
Sodium and other ions that do not penetrate into the passivation film 5 adhere to the surface of the passivation film 5. Since the passivation film 5 is extremely thin, for example, about 0.1 to 0.5 μm, a local electric field generated by the adhered ions distorts the distribution of an electric field in the vicinity 42 of the end 15 of the p-n junction. Such a phenomenon may cause a local change of a p-type into an n-type or a local change of an n-type into a p-type. This phenomenon is called generation of an inversion layer. As a result of the generation of the inversion layer, part of the p-n junction is extremely thinned and causes an increase in dark current due to breakdown. The noisy dark current causes deterioration of the receiving characteristics and inhibits receiving high-frequency pulse signals.
It is well known that mobile ions such as sodium ions adhered to the photodiode increase a dark current. Thus, after the p-n junction and the passivation film of the photodiode are formed, a final chip making step and a packaging step are normally performed in a clean environment to prevent contamination to the extent possible.
The new process, in which PD chips are fixed onto an Si wafer and then dicing is carried out to separate the wafer into the PD chips, will cause new problems as described above, i.e., contamination at the vicinities 42 of the ends of the p-n junction and the exposed portions 18, and an increase in dark current. Such a process has never been performed, however; hence, the above problems are not actually observed. Dicing involves mechanical cutting in which a lubricant oil and an abrasive agent (including abrasive powder and chemical agent) are applied and a rotating blade is brought into direct contact with the wafer; hence, the PD will be significantly contaminated.